(a) Field of the Invention
The present invention relates to a multiplying digital to analog converter, and more particularly, relates to a multipath pipelined analog to digital converter using the same.
(b) Description of the Related Art
A multipath pipelined analog to digital converter realizes high-speed performance by sequentially processing one sample and hold output through each path and sequentially outputting the processed output through a multiplexer (MUX).
Hereinafter, a multiplying digital to analog converter is referred to as a MDAC, and an analog to digital converter is referred to as an ADC throughout the specification.
FIG. 1 is a conceptual scheme of a general pipelined ADC.
Referring to FIG. 1, a function of the MDAC, which is a pipelined ADC, will be described in detail.
The pipelined ADC digitalizes an analog input signal (AIN) in increments over multiple stages ST1 to STk. Within each stage, a sample and hold amplifier (SHA) 10, an n-bit ADSC (sub-ADC) 20, an n-bit DASC (sub-DAC) 30, and an adder 40 are included. The SHA 10 receives an analog signal Ri-1 of a previous stage, and holds the analog signal Ri-1 for a defined period of time after sampling it. The n-bit ADSC 20 converts the sampled analog signal Ri-1 into a digital signal and outputs the digital signal. The n-bit DASC 30 converts the digital signal output from the n-bit ADSC 20 into an analog signal. The adder 40 adds the analog signal output from the n-bit DASC 30 and the previous stage analog signal passed through the sample and hold amplifier 10, and generates an analog signal Ri to be input to a SHA 10 of a next successive stage.
For example, each stage processes 4-bit analog to digital convergence as follows. A 4-bit ADSC 20 receives an input analog signal and outputs a 4-bit digital signal. A 4-bit DASC 30 receives the 4-bit digital signal and converts it into an analog signal. The adder 40 substrates the analog signal outputted from the 4-bit DASC 30 from the analog signal outputted from the SHA 10, which corresponds to the analog signal outputted from the previous stage. Then, the adder 40 outputs the result analog signal as an analog signal for the next successive stage
In each stage, the n-bit DASC 30, the adder 40, and the SHA 10 are provided in a format of the MDAC, except for the n-bit ADSC 20. In this case, each stage is configured with the sub-ADC and MDAC.
Stage redundancy in the multipath pipelined analog to digital converter is exploited to convert a portion of an analog signal into a digital signal for desired signal conversion.
FIG. 2 shows a general multipath pipelined ADC.
FIG. 2 conceptually illustrates a 10-bit multipath pipelined ADC having a first path 50 path1 and a second path 60 path2, different from the pipelined ADC of FIG. 1.
Considering that the operation speed of a MDAC block in each stage affects the speed of all the ADCs, the multipath pipelined ADC processes the same amount of data even though the operation speed is set to be half as much as that of a single path ADC because a signal sampled through a sample and holding circuit is alternately transmitted to the first path path1 and the second path path2 to be processed.
However, when using multiple paths, an offset between the paths may be differentiated and thus each path may output different digital signals in response to the same analog signal input, thereby causing degradation of resolution. Therefore, most of the multipath pipelined ADCs employ a calibration circuit for calibrating differential offsets between the multiple paths.
The calibration circuit stores an offset difference between the paths when no signal is input, and subtracts/adds a digital value from/to an output of each path corresponding to the offset difference when a signal is input to calibrate the differential offsets between the paths. In other words, the conventional multipath pipelined ADC estimates a DC offset between the paths to calibrate an estimated amount of offsets in one of the paths, or stores a code difference between the paths in a memory to calibrate the code difference while operating the calibration circuit. Such a calibrating method requires additional operations to estimate offsets between the paths and adds circuit complexity to calibrate the offsets, thereby increasing cost.
The U.S. Pat. No. 5,294,926 discloses a method for removing error factors in multiple paths by using a calibration algorithm. However, the method has a problem of requiring a plurality of circuits for realizing the calibration algorithm thereby increasing cost.
Another type of calibration circuit is disclosed by L. Sumane (entitled “A 10 bit 200 MS/s CMOS Parallel A/D converter”, IEEE JSSC, Vol. 36, No. 7, pp 1048˜1053, July, 2001). The circuit, including a register in an ADC output to remove an offset in a multipath ADC, stores on offset in each path, and calibrates a digital value corresponding to the offset in each path in the ADC output. However, the circuit requires an additional circuit for removing the offset and additional operations for estimating and removing the offset.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention, and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known in this country to a person of ordinary skill in the art.